The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures.
Complementary metal-oxide semiconductor (CMOS) circuitry is utilized in mobile communication devices (e.g., laptops, cellular phones, tablets, etc.) to handle wireless high frequency signals transmitted to and/or received by the mobile communication devices. The circuitry may include a high frequency switch that allows for high frequency signals received by an antenna to be routed from a low noise amplifier to other chip circuitry and for high frequency signals to be routed from a power amplifier to the antenna. The high frequency switch may include a stack or bank of field effect transistors formed by CMOS processes.
A back-end-of-line (BEOL) interconnect structure may be used to route signals to and from the active devices of an integrated circuit, such as a switch of a CMOS integrated circuit. The BEOL interconnect structure may include wiring embedded in a stack of dielectric layers to create a stack of wiring levels defining an interconnection network for the signals and power. The BEOL interconnect structure may be fabricated using damascene processes in which the different wiring levels in the stack are individually formed.
Chip structures with improved wiring layouts and fabrication methods for forming such chip structures are needed.